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Home > Archive > Electrical Engineering > May 2007 > Question about D-flop
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Question about D-flop
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| I'm looking at a datasheet for a CD4013BC D-flip flop.
The current for a high output states -0.36mA @ 5volts
Three questions:
Why is a high output called negative current when I would think it's
positive.
This is the absolute highest current (at 5-volts) the outputs can drive?
If the quiescent current of the overall device is 30uA, how can I calculate
the peak current when it's driving a load? Would it be as simple as 0.36mA
+ 30uA???
Thanks in advance.
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Peter wrote:
> I'm looking at a datasheet for a CD4013BC D-flip flop.
>
> The current for a high output states -0.36mA @ 5volts
OK, although that value is really for 125 degrees C...that is HOT!
Room temperature minimum is .51 mA with a typical value (means some
packs will do it) of .88 mA.
> Three questions:
>
> Why is a high output called negative current when I would think it's
> positive.
This is because the packs are TTL compatible. In a TTL pack the input
is an emitter and hence current flows OUT of the input and INTO the
Cmos output for a LOW. This is why convention is reversed. Since
sinking current (low) is standard it's given a positive sign. Sourcing
current (High) is in the reverse direction.
> This is the absolute highest current (at 5-volts) the outputs can drive?
No, as noted above it drives more at room temp and some packs will
drive even a bit more. If you go to 10 or 15 volt VDD you can drive up
to 3.4 mA. A couple of mA is typical of what CMOS packs do with 10 or
15 volt VDD. If you need more you have to add a driver or go to a
buffered pack.
> If the quiescent current of the overall device is 30uA, how can I calculate
> the peak current when it's driving a load? Would it be as simple as 0.36mA
> + 30uA???
Yes and no. If you are simply figuring a DC drain from VDD then you
just add. This is sourcing current from VDD. If you are sinking
current (like from TTL) then the current comes from the TTL and
doesn't come from VDD. If you are switching at fast rates then the VDD
drain rises because of the internal switching even with no external
current sourcing. So "peak" current has a time dependent component
here. Note that if you are operating a CMOS gate (which will not be
the case with a D flop) as a linear device they draw more current in
the transition region.
> Thanks in advance.
Hope this helps.
Benj
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| Benj <bjacoby@iwaynet.net> wrote in
news:1180499697.857021.73870@o5g2000hsb.googlegroups.com:
>
> Peter wrote:
>
> OK, although that value is really for 125 degrees C...that is HOT!
> Room temperature minimum is .51 mA with a typical value (means some
> packs will do it) of .88 mA.
>
>
> This is because the packs are TTL compatible. In a TTL pack the input
> is an emitter and hence current flows OUT of the input and INTO the
> Cmos output for a LOW. This is why convention is reversed. Since
> sinking current (low) is standard it's given a positive sign. Sourcing
> current (High) is in the reverse direction.
>
>
> No, as noted above it drives more at room temp and some packs will
> drive even a bit more. If you go to 10 or 15 volt VDD you can drive up
> to 3.4 mA. A couple of mA is typical of what CMOS packs do with 10 or
> 15 volt VDD. If you need more you have to add a driver or go to a
> buffered pack.
>
>
> Yes and no. If you are simply figuring a DC drain from VDD then you
> just add. This is sourcing current from VDD. If you are sinking
> current (like from TTL) then the current comes from the TTL and
> doesn't come from VDD. If you are switching at fast rates then the VDD
> drain rises because of the internal switching even with no external
> current sourcing. So "peak" current has a time dependent component
> here. Note that if you are operating a CMOS gate (which will not be
> the case with a D flop) as a linear device they draw more current in
> the transition region.
>
>
> Hope this helps.
>
> Benj
>
>
I'll read this more in-depth after a good night of sleep. Our problem is:
we're trying to show a logical 1 or 0 on an evaluation board at89c5131_ds
Both Q and Q bar of the D-flop are driving 10k resistors to a 3904 to turn
on (and off) LEDs while there is a direct connection from the Q and Q bar
outputs to the evaluation board.
My guess: the outputs can't drive both the transistor and evaluation board,
however, I can't totally prove this because the evaluation board spec sheet
appears to take very low current.
Thanks again
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Peter wrote:
> Both Q and Q bar of the D-flop are driving 10k resistors to a 3904 to turn
> on (and off) LEDs while there is a direct connection from the Q and Q bar
> outputs to the evaluation board.
Which means you are already close to pulling the max current levels
with just the 3904!
> My guess: the outputs can't drive both the transistor and evaluation board,
> however, I can't totally prove this because the evaluation board spec sheet
> appears to take very low current.
As a general rule unbuffered CMOS logic usually only easily drives
other CMOS logic. If you want to really drive some current you need
some kind of external output stage. A 3904 (or better 2222) is the
standard thing, but I find that small cheap FETs do better because
they have some decent current ratings and don't suck a ton of gate
current.
Since you've already put the 3904 there, so drive the evaluation board
from the 3904 like God intended!
Good Luck!
Benj
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